1. Field of the Invention
The present invention generally relates to an improved isolation trench geometry for trenches formed in silicon-on-oxide wafers, and more particularly to a geometry that reduces structural stress in the trench wall, and includes a process for forming such isolation trenches.
2. Description of the Prior Art
Building semiconductor devices on silicon-on-insulator (SOI) wafers is recent technology that has been introduced to improve circuit speed and device reliability. Depending on the circuit application, the thickness of the top silicon layer of a silicon-on-insulator wafer will vary from 0.05 .mu.m to 15 .mu.m. Normally, SOI device applications can be divided into three categories: (a) high density, low power digital CMOS applications where a thin silicon layer (about 0.05 to 0.2 .mu.m) is desirable to form fully depleted MOS devices; (b) medium density, high speed and low voltage digital BiCMOS applications where a silicon thickness of 1.5 to 3.0 .mu.m is needed in order to achieve optimum bipolar performance, i.e., high cut-off frequency; and (c) low density, high speed and high voltage analog BiCMOS devices where a large silicon thickness ranging from 8 to 15 .mu.m is necessary in order to withstand high voltage operation.
Since each of these three SOI devices requires a different range of silicon layer thickness and different integrated device density, quite different isolation schemes are needed. For case (a) with the thin SOI, the isolation is usually formed by using a conventional recess oxidation (ROX) process. For Case (b) with the medium thickness SOI, trench isolation with an oxide sidewall and polysilicon fill is used. Lastly in case (c) with the thick SOI where there is a power limitation which allows only low density integration, simple junction isolation is adequate.
In cases (a) and (b), the prior art isolation recess or trench can develop regions of large stress. Ion implantation in these stress regions can result in a nucleate glide dislocation that can cause shorts or leakage in transistors.